1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a bit line of a semiconductor device and its manufacturing method.
2. Description of the Background Art
As the density of integrated devices is increased, elements of the integrated devices become smaller. Accordingly, a bit line, one of the elements of the integrated device, is reduced in its cross-sectional area. This causes the resistance of the bit line to increase. To solve the problem, it is known to form the bit line of a metal. Tungsten is typically used as the metal wiring material.
FIGS. 1A through 1G show a sequential method for manufacturing a bit line using tungsten according to the background art.
First, as shown in FIG. 1A, on a semiconductor substrate 1 where a device isolation, a well formation and a planarization was performed, a layer-insulation layer 3 is deposited. Then a photo-etching process is performed by using a photoresist (not shown) as a mask to form a contact hole 5 in a predetermined region of the layer-insulation layer 3.
Then, as shown in FIG. 1B, cleaning is performed in order to remove a foreign substance such as a native oxide (not shown) existing at the bottom surface of the contact hole 5. And then, a diffusion barrier 7 formed of a multi-film of Ti/TiN is formed on the upper portion of the layer-insulation layer 3 and on the inner side of the contact hole 5.
Thereafter, thermal treatment is performed to form a silicide layer 9 in the vicinity of the interface of the semiconductor substrate 1 and the diffusion barrier 7. The silicide layer 9 serves to reduce a contact resistance between the semiconductor substrate 1 and the bit line. After formation of the silicide layer 9 through the thermal treatment, a titanium nitride is additionally deposited on the upper surface of the diffusion barrier 7.
And then, as shown in FIG. 1C, a first tungsten layer 11 is thickly formed on the diffusion barrier 7 and inside the contact hole 5 by a chemical vapor deposition (CVD) method. The first tungsten layer 11 completely fills the contact hole 5.
Next, as shown in FIG. 1D, the first tungsten layer 11 is removed by etching back or by chemical mechanical polishing (CMP) so that the upper surface of the diffusion barrier 7 is exposed, to thereby form a tungsten plug 11xe2x80x2.
Then, as shown in FIG. 1E, a titanium nitride layer 13 is formed on the upper surface of the tungsten plug 11xe2x80x2 and of the diffusion barrier 7.
And then, as shown in FIG. 1F, a second tungsten layer 15 is formed on the upper surface of the titanium nitride layer 13 for a line. The second tungsten layer 15 is deposited by the chemical vapor deposition method, for which SiH4 is used as a deoxidation gas in the initial stage of the deposition and H2 is used as a deoxidation gas in the later stage of the deposition.
The tungsten layer deposited by using SiH4 as a deoxidation gas is disadvantageous in that its resistivity is high and a step coverage is bad. Meanwhile, in case of the tungsten layer deposited by using H2 as a deoxidation gas, its resistivity is low and a step coverage is satisfactory. But, in case of the tungsten layer deposited by using the tungsten layer using H2 as a deoxidation gas, since it is not evenly deposited on the titanium nitride layer, a tungsten layer is deposited with the thickness of 200 xc3x85xcx9c500 xc3x85 in the initial stage of deposition of the second tungsten layer by using SiH4 as deoxidation gas.
Subsequently, a photoresist film is coated on the upper surface of the second tungsten layer 15 and patterned to form a photoresist film pattern 17.
Next, as shown in FIG. 1G, the second tungsten layer 15, the titanium nitride layer 13 and the diffusion barrier 7 are sequentially etched by photo-etching process using the photoresist film pattern 17 as a mask, so as to form a bit line 20. The bit line 20 is part of a bit conductor structure 22 that also includes the tungsten plug 11 and the titanium nitride layer 13. The diffusion barrier 7 positioned at the corner portion of the contact hole 5 is a bit excessively etched during the photo-etching process.
Finally, the photoresist film pattern 17 which was used as a mask is removed, thereby completing the manufacturing process of bit line in accordance with the conventional art.
The method for manufacturing the bit line in accordance with the background art has problems in that since the plug and the line are separately formed, the manufacturing process is complicated and the unit cost of the device is increased. Also, since particles are increasingly generated during the process, the yield rate is lowered.
In addition, according to the method for manufacturing the bit line in accordance with the background art, the tungsten layer 15 for forming the line is formed on the titanium nitride. Therefore, when the tungsten layer 15 is deposited by the chemical vapor deposition method, SiH4 is used as a dioxidation gas at the initial stage of the deposition and H2 is used as a dioxidation gas at the later stage of the deposition, the manufacturing process is complicated. Also, the tungsten layer deposited by using SiH4 as a dioxidation gas has a high resistivity and undesirable step coverage, degrading the characteristics of the bit line.
Moreover, in the method for manufacturing the bit line in accordance with the background art, the tungsten layer 15 is deposited by the chemical vapor deposition method which uses WF6 as a source gas. In this respect, there is a high possibility that fluorine (F) of the source gas etches the silicon forming the semiconductor substrate and SiF1 is thereby formed, leading to an increase in the contact resistance of the bit line and the leakage current.
Therefore, an object of the present invention is to provide a bit line and its manufacturing method which are capable of simplifying the manufacturing process of the bit line, and of improving yield by reducing the amount of particles generated during its process, thereby lowering unit cost.
Another object of the present invention is to provide a bit line and its manufacturing method which are capable of improving electric characteristics of a bit line by reducing the amount of a diffusion barrier that is formed in the bit line, the diffusion barrier layer having a higher resistivity than tungsten.
Still another object of the present invention is to provide a bit line and its manufacturing method which are capable of removing the necessity to deposit a tungsten layer on a titanium nitride layer by chemical vapor deposition, so that there is no need to use SiH4 as a dioxidation gas, and thus, characteristics of the tungsten layer can be highly improved.
Yet another object of the present invention is to provide a bit line and its manufacturing method which are capable of resolving the problem that WF6 (when used as a source gas for a tungsten layer deposited by chemical vapor deposition) etches silicon or reacts with the silicon to degrade the characteristics of the bit line.
To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described herein, there is provided a bit line including: substrate including semiconductor material; a layer-insulation layer formed on the upper surface of the substrate with a contact hole therein; a metal layer reacting with the substrate exposed by the contact hole; a silicide formed where the metal layer contacts the substrate; a nitride layer formed on the upper surface of the metal layer; a first conductive layer (having attributes that are characteristic of being formed by a first deposition technique) formed on the upper surface of the nitride layer, the first conductive layer being made of a metal; and a second conductive layer (having attributes that are characteristic of being formed by a second deposition technique) formed on the upper surface of the first conductive layer, the second conductive layer being made of a metal.
In order to achieve the above objects, there is provided a method for manufacturing a bit line, the method including: forming a layer-insulation layer on the surface of a substrate that includes semiconductor material; forming a contact hole on a predetermined region of the layer-insulation layer; forming a diffusion barrier inside the contact hole; forming a first conductive layer on the upper surface of the diffusion barrier; forming a second conductive layer on the upper surface of the first conductive layer; wherein the first and second conductive layers are formed by different deposition techniques; and patterning the first and the second conductive layers.